Field of the Disclosure
The present disclosure relates generally to semiconductor devices and, more particularly, to trench gate field effect transistors.
Description of the Related Art
Trench gate field effect transistors (FETs) frequently are utilized in high-voltage applications. Such transistors often leverage the reduced surface field (RESURF) effect to achieve a relatively low on resistance (RDSon) while maintaining a relatively high breakdown voltage (BVdss). RESURF-based trench gate architectures employ a one-dimensional or two-dimensional array of cells formed in an active region of an epitaxial layer that overlies a substrate that serves as part of a drain electrode structure. Each cell includes a trench extending into the epitaxial layer, with each trench including a gate electrode structure formed therein. Well regions are formed in the mesa regions of the epitaxial layer between the trenches, and a source electrode is connected to the channel regions via a source contact region. The trench gate design also may employ a termination region at a periphery or one or more edges of the active region so as to provide effective edge termination by spreading out the electric field at the edges of the active region. Conventional trench gate FET designs provide edge termination through the use of field rings or field plates. However, the formation of these structures require a significant number of additional process steps during the fabrication process, thus increasing the cost and complexity of manufacturing semiconductor devices based on these designs.